1. Field
This disclosure relates to a semiconductor device, in particular, to High Electron Mobility Transistors (HEMTs), and a method of making the same. This disclosure describes an improved device and an improvement to a process for fabrication of ohmic contacts to GaN/AlGaN HEMTs using a novel two step resist process to fabricate the ohmic contacts.
2. Description of the Related Art
A semiconductor in which the concentration of charge carriers is characteristic of the material itself rather than of the content of impurities and structural defects of the crystal is called an intrinsic semiconductor. In an ideal intrinsic semiconductor, mobility is determined by lattice scattering; that is, collisions between lattice waves (phonons) and electron waves (electrons). In an actual intrinsic specimen there are always some atomic impurities that may dominate scattering at low temperatures when phonons are quiescent, but at higher temperatures lattice scattering, particularly by optical phonons, is dominant. At cryogenic temperatures (e.g., T=4° K to 77° K) ionized impurity scattering does indeed dominate mobility. In addition, the theory of Brooks and Herring predicts, and experimentation confirms, that as a result of electron-electron scattering at a given temperature, mobility decreases with increasing impurity concentration, and for each doping level there is a theoretical maximum mobility.
The prior art, known to the inventors, that is improved by this invention is the current process for fabricating GaN HEMT ohmic contacts. In the prior art, GaN HEMT ohmic contact fabrication process, the baseline GaN HEMT structure shown in FIG. 1, consists of, starting at the substrate 10, a 10-20 nm thick AIN or AlyGa(1-y)N nucleation layer 11a, a 250 nm to 4000 nm thick GaN layer 11b and a 10 nm to 40 nm thick strained AlGaN Schottky barrier layer 11c. The Al content x in a ternary AlxGa(1-x)N Schottky barrier layer 11c could be any value between 0.1 and 0.4. For the purpose of the following discussion of the prior art, an x value of 0.3 and a Schottky barrier 11c thickness of 30 nm is chosen. The mobile two dimensional electron gas (2DEG) charge at the AlGaN/GaN interface is obtained by piezoelectric and spontaneous polarization due to lattice mismatch induced strain between the GaN 11b and the AlGaN Schottky barrier layer 11c, and not by doping. The electron charge density is roughly proportional to Al content x in the Schottky barrier layer 11c (strain) and thickness of the Schottky barrier 11c, (due to less surface charge depletion). It was empirically established that the best combination of the 2DEG sheet charge and specific ohmic contact resistance is obtained for x values between 0.15 and 0.3 and Schottky barrier 11c thickness between 20 nm and 40 nm. The upper value of x and the thickness of the Schottky barrier 11c is limited by the fact that barriers with an x value higher than 0.3 give poor ohmic contacts, and that strained barriers thicker than 40 nm can not be grown due to strain relaxation.
The fabrication process of the prior art is discussed as follows. In a first fabrication process, the source and drain contact pad areas are defined into a first photoresist using an image reversal process. FIG. 2 shows a typical layout of source 12 and drain 13 pads of a GaN power HEMT. The separation between the source 12 and drain pads 13 shown in the prior art process is 2 μm. An image reversal process is used to obtain under-cut of the photoresist 14 as shown in FIGS. 3 and 4. The photoresist ledge 15 that is created by the undercut acts as a shadow mask during high vacuum metal evaporation and prevents metal from depositing onto the photoresist side-walls 16. The photoresist profile undercut obtained by the prior art process is approximately 0.25 μm.
During the next fabrication step, as shown in FIG. 3, the Schottky barrier layer 11c is etched by Chlorine plasma in a Reactive Ion Etching (RIE) system to reduce the Schottky barrier thickness. This step is called ohmic recess etching, and regions in which the Schottky barrier is etched are called recessed areas 17. It was empirically established that ohmic contact resistance is minimized when the Schottky barrier layer 11c is thinned to between 7.5 nm and 10 nm. The cross section of the device structure formed by the steps up to this point is shown in FIG. 3. A structure with a thinner 7.5 nm to 10 nm thick Schottky barrier that would not require a RIE etching step is, unfortunately, not suitable for fabrication of GaN HEMTs, because its 2DEG sheet charge is too low for semiconductor device applications. By using the ohmic recess etch process, the 2DEG sheet charge is reduced only in recessed areas 17.
The semiconductor structure, after ohmic recess etching, is loaded into a high vacuum e-beam evaporator and ohmic metals 18 are evaporated in the following sequence: 20 nm Ti, 200 nm Al, 50 nm Ni and 50 nm Au. The cross section of the device structure after this step is shown in FIG. 4. This figure also illustrates that the prior art process provides for unprotected recessed areas 17a, which is its major flaw. The unprotected recessed areas 17a are not covered by the ohmic metals 18. The unprotected recessed areas 17a have adverse effects on performance and reliability of GaN HEMTs because 2DEG sheet charge in these areas is by almost a factor of three lower than sheet charge in areas not etched by Cl plasma. The low 2DEG sheet charge in unprotected recessed areas is too low to support high current densities typical for GaN HEMTs. It is reasonable to assume that high electric fields and electron velocity saturation arise in these areas at high current densities, just as they do underneath the gate of the device. The presence of the second high field region in a HEMT degrades frequency response, power-added efficiency, and power handling capability of the device. It also contributes to needless heating of the device, and hence accelerates device degradation. Device performance would be improved by elimination of unprotected recessed areas.
The photoresist 14 is lifted off by a 1-hour soak in a mild photoresist stripper at 100° C. and rinsing in DI water. Photoresist residues are not completely removed during the lift-off process. The presence of photoresist residues after ohmic metal lift-off is the second major weakness of the prior art ohmic contact fabrication process. Attempts to completely remove these residues by extended soak in a mild photoresist stripper are unsuccessful. A soak in a harsh photoresist stripper removes these residues, but it unfortunately attacks the ohmic metal.
The fabrication of ohmic contacts 19, is concluded by a 30 second rapid thermal anneal (RTA) at 875° C. in nitrogen as shown in FIG. 5. In FIG. 5, the device cross section after RTA is shown. During this high temperature anneal, according to current theories of n-type GaN ohmic contacts, an AlTiN alloy with low Schottky barrier height is converted to heavy n-type AlGaN through a chemical reaction between ohmic metal and underlying semiconductor films. The formation of ohmic contacts is facilitated by the fact that GaN and AlGaN layers underneath the ohmic metal are due to loss of nitrogen converted to heavy n-type material 20, as nitrogen vacancies become donors in these Group III V semiconductors. The electrical properties of GaN HEMT layers not covered by the ohmic metal during high temperature anneal are, due to absence of the chemical reaction, not significantly altered during this step. Photoresist residues, mentioned above, melt and flow during high temperature annealing and leave residues in the active area of the device. These residues get buried underneath the gate metal during subsequent processing steps. It is not clear at this moment how presence of these residues under the gate metal affects performance of the devices. However, it is well documented in the literature that impurities underneath the gate metal adversely affect the performance of field effect transistors (FETs).
The disadvantages of the prior art process include incomplete coverage of the recessed areas by the ohmic metals. The low 2DEG sheet charge in unprotected recessed areas 17a is too low to support high current densities typical for GaN HEMTs. It is reasonable to consider that high electric fields and electron velocity saturation arise in these areas at high current densities, just as they do underneath the gate of the device. The presence of a second high field region in a HEMT degrades frequency response, power-added efficiency, and power handling capability of the device. It also contributes to needless heating of the device, and hence accelerates device degradation. Furthermore, this prior art process leaves photoresist residues in the active areas of the device. It is common knowledge, for people skilled in the art of semiconductor devices, that impurities underneath the gate metal adversely affect the performance of field effect transistors (FETs).